FS_DIRTY=3<<13,// FPU registers dirty (and must be saved on context switch)
XS=3<<15,// Extension Status
XS_OFF=0<<15,// Extension off
XS_INIT=1<<15,// Extension on
XS_CLEAN=2<<15,// Extension registers clean
XS_DIRTY=3<<15,// Extension registers dirty (and must be saved on context switch)
MPRV=1<<17,// Memory PRiVilege (when set, enables MMU also in machine mode)
SUM=1<<18,// Supervisor User Memory access allowed
MXR=1<<19,// Make eXecutable Readable
TVM=1<<20,// Trap Virtual Memory makes SATP inaccessible in supervisor mode
TW=1<<21,// Timeout Wait for WFI outside machine mode
TSR=1<<22,// Trap SRet in supervisor mode
SD=1<<31,// Status Dirty = (FS | XS)
};
// Interrupt-Enable, Interrupt-Pending and Machine Cause Registers (mie, mip, and mcause when interrupt bit is set)
enum{
SSI=1<<1,// Supervisor Software Interrupt
MSI=1<<3,// Machine Software Interrupt
STI=1<<5,// Supervisor Timer Interrupt
MTI=1<<7,// Machine Timer Interrupt
SEI=1<<9,// Supervisor External Interrupt
MEI=1<<11// Machine External Interrupt
SSI=1<<1,// Supervisor Software Interrupt
MSI=1<<3,// Machine Software Interrupt
STI=1<<5,// Supervisor Timer Interrupt
MTI=1<<7,// Machine Timer Interrupt
SEI=1<<9,// Supervisor External Interrupt
MEI=1<<11// Machine External Interrupt
};
// Exceptions (mcause with interrupt = 0)
...
...
@@ -76,7 +93,7 @@ public:
classContext
{
public:
// Contexts are loaded with mret, which gets pc from mepc and updates some bits of mstatus, that's why _st is initialized with MPIE and MPP
// Contexts are loaded with [m|s]ret, which gets pc from [m|s]epc and updates some bits of [m|s]status, that's why _st is initialized with [M|S]PIE and [M|S]PP
